This application claims priority to an application entitled xe2x80x9cApparatus for Controlling Time Deinterleaver Memory for Digital Audio Broadcastingxe2x80x9d filed in the Korean Industrial Property Office on Aug. 30, 2000 and assigned Serial No. 2000-50700, the contents of which are hereby incorporated by reference.
1. Field of the Invention
The present invention relates generally to a digital audio broadcasting (DAB) system, and in particular, to a method and apparatus for controlling a time deinterleaver memory in a DAB system.
2. Description of the Related Art
In a DAB system, a transmitter interleaves a signal before transmission and a receiver then deinterleaves the interleaved signal received from the transmitter. In the interleaving process, the transmitter sequentially writes transmission data in an interleaver memory, reads the written data in a predetermined sequence, and then transmits the read data. In this interleaving process called xe2x80x9ctime interleaving processxe2x80x9d, the data is delayed for up to 16 frames (1 frame=55296 bits), so that data input to the interleaver will be distributed over 16 frames when it is output. Therefore, to time-deinterleave the time-interleaved data, the receiver writes 16-frame data in a deinterleaver RAM (Random Access Memory) and then reads the written data according to a deinterleaving rule matched to the interleaving rule used in the transmitter.
FIG. 1 illustrates an address controller for generating addresses used to read and write data from and into a deinterleaver RAM to deinterleave the interleaved data transmitted from the transmitter in the DAB system. The address controller includes a counter 20, a bit inversion block 22, an A decoder 24, a B decoder 32, a ROM (Read Only Memory) 26, an adder 28 and a multiplier 30. In the deinterleaving process, the receiver writes the first received 16 frames in a deinterleaver RAM, and then writes a next received frame after reading one written frame. More specifically, the interleaved 16-frame data is first written in the deinterleaver RAM. Subsequently, the deinterleaver address controller generates a memory read address to read one data frame written in the deinterleaver RAM. The counter 20 counts data bits received at the deinterleaver. The B decoder 32 alternately switches between a read mode and a write mode in a frame unit, after the first 16 frames. In the read mode, the bit inversion block 22 bit-inverts a count value provided from the counter 20. The A decoder 24 decodes the bit-inverted binary value output from the bit inversion block 22 and outputs the decoded binary value to the ROM 26, in which position information of the data bits within one frame is written. The ROM 26 outputs position information of the data bits output from the A decoder 24. The multiplier 30 converts, in a bit unit, information on a value determined by performing a modulo-16 operation on a frame value (or frame number) to which the present data belongs. That is, the multiplier 30 generates a reference address used in reading a data bit from the deinterleaver RAM. The reference address is added by the adder 28 to the bit position information from the ROM 26, and the added value becomes the final read address to be used in reading the data written in the deinterleaver RAM. The deinterleaver reads out the data written in the deinterleaver memory according to the read address. After completion of performing the read process on one interleaved data frame, the deinterleaver is switched to the write mode by the B decoder 32 and writes one data frame. In this way, the deinterleaver alternates between the read mode and the write mode on a 1-frame unit basis, after the first 16 data frames.
For the time deinterleaving, the address controller needs a memory with a capacity sufficient to store the 16 data frames. If one symbol input to the deinterleaver is data subjected to 4-bit soft decision, 55296 bitsxc3x9716 framesxc3x974 bits=3.375 Mbits. In this case, the address controller requires a 4-Mbit memory. This means that the DAB receiver must include a 4-Mbit memory, increasing the cost of the product.
It is, therefore, an object of the present invention to provide a method and apparatus for controlling a time deinterleaver for digital audio broadcasting (DAB), capable of reducing a required minimum memory capacity of a DAB receiver.
To achieve the above and other objects, there is provided a method of generating addresses for writing and reading interleaved data in a deintervleaver memory, including the steps of associating preselected frames of the deinterleaver memory with each other to reduce a required memory capacity, calculating head positions of locations for the frames in the deinterleaver memory, and writing data bits into the deinterleaver memory at the calculated head positions. After all the frames are written into the deinterleaver memory, one frame is read from the plurality of frames and one frame is written to the deinterleaver memory for every frame read from the deinterleaver memory.
An apparatus is also provided for controlling a deinterleaver memory, the apparatus generating addresses for writing and reading interleaved data transmitted from a transmitter into/from the deinterleaver memory having a plurality of memory areas associated with a plurality of frames of the interleaved data. The apparatus comprises an encoder for outputting, upon receipt of frame information for a first set of frames, frame information for a second set of frames to write the first set of frames in unused memory areas, allocated for the second set of frames, out of the memory areas of the deinterleaver memory; and a ROM in which bit position information of the memory areas for the frames are written such that the memory areas for the first set of frames should not be overlapped with the memory areas for the second set of frames.